This section introduces aspects that may help facilitate a better understanding of embodiments of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
When a memory device having an array of SRAM (static random-access memory) bitcells is to be accessed (e.g., data written to or read from one or more rows of bitcells in the array), the entire array of bitcells in the memory device is configured in a so-called active mode with (i) the power supply voltage VDD applied to the drain nodes of certain p-type MOS (metal-oxide semiconductor) transistors in each bitcell in the array and (ii) a lower, ground voltage VSS applied to the source nodes VSSC of certain n-type MOS transistors in each bitcell in the array to enable the transistors to be turned on and off with appropriate control voltages applied to their gates.
In order to reduce power consumption due to leakage currents through the bitcells when access to such a memory device is not needed, it is known to bias the source nodes VSSC of such bitcells to an appropriate intermediate, data-retention voltage level between the ground voltage VSS and the power supply voltage VDD to place the memory device into a sleep mode in which the memory array cannot be accessed, but will retain data previously stored therein. Bias circuitry is provided to control the application and removal of such source bias voltages to enable the memory device to be selectively configured in either its sleep mode or its active mode.